A network on a chip (NOC) is a novel integrated circuit architecture that applies a network-based architecture to a single chip to create a unique processing unit. A typical NOC includes a plurality of integrated processor (IP) blocks coupled to one another via an on-chip network. NOC processing units typically distribute (i.e., allocate) various parts of a job to different hardware threads of one or more IP blocks to be executed by the one or more IP blocks in the NOC processing unit, where the distribution typically includes transmitting data packets including one or more data words between one or more hardware threads of the NOC. With the number of IP blocks in the standard computer systems expected to rise, efficiently handling workload distribution has become increasingly demanding.
In many conventional NOC architecture systems, inter-thread communication is performed by transmitting data packets (“messages”) between hardware threads using the on-chip network. In some NOC architecture systems, an inbox/outbox model is used, whereby transmitting data packets is often referred to as “message passing,” and conventionally a message (i.e., a data packet) is transmitted from an output buffer (i.e., an “outbox”) of a first hardware thread to an input buffer (i.e., an “inbox”) of a second hardware thread over the network of the NOC. Such conventional implementations are typically referred to as “direct inter-thread communication” messaging (hereinafter “DITC”). As such, each hardware thread of a DITC implementation includes inter-thread communication hardware resources (e.g., an inbox and an outbox) connected to the on-chip network. In other NOC systems, various other inter-thread communication hardware resources are utilized to facilitate message passing on the on-chip network. Generally, these inter-thread communication hardware resources associated with a hardware thread receive messages from the network and the data is received from the resource into an execution register file connected to an execution unit of a hardware thread such that the data may be processed by the execution unit during execution of instructions. Similarly, following processing, output data may be sent to a inter-thread communication hardware resource for communication to one or more other hardware threads via the on-chip network.
Inter-thread communication via inter-thread communication hardware resources has generally led to increased workload distribution efficiency. However, in some situations, data passed in messages on the on-chip network using inter-thread communication hardware resources is generally not secured. As such, hardware threads executing instructions on behalf of a low-level processes may corrupt data buffers of inter-thread communication hardware resources by moving data to and from buffers of inter-thread communication hardware resources. As such, in many NOC architectures, inter-thread communications may be reserved for hypervisor or supervisor features and not for user mode processes to prevent user mode processes from potentially corrupting buffers associated with inter-thread communication hardware resources.
In addition, due to the increasing numbers of threads being supported in typical processing units, security of confidential data, even among different threads on the same chip, becomes more important, particularly, for high security applications, since different threads in the same processing unit may be executing different processes on behalf of completely different users, providing a potential avenue for a malicious process running on one thread to attack another process running on a different thread.
Therefore, a continuing need exists in the art for a manner of securing data in inter-thread network communication architectures such as NOC architectures.